The present invention relates to a technique which can be especially effective when applied to an internal booster circuit in a semiconductor integrated circuit, and more particularly to a technique which can be effectively applied to, for instance an internal booster circuit in a nonvolatile memory in which stored information can be electrically erased.
A flash memory uses as its memory cell a nonvolatile memory element consisting of a MOSFET of a double gate structure having a control gate and a floating gate, wherein the threshold voltage of the MOSFET can be varied and information can be stored by altering the fixed electric charge of the floating gate. In such a flash memory, writing or erasing any content into or out of memory cells requires a high voltage (e.g. xc2x110 V or more) to vary the threshold voltage by withdrawing (or ejecting) or injecting an electric charge out of or into the floating gate of the nonvolatile memory element. It is usual in a flash memory to generate such a high voltage from an internal booster circuit provided in a memory chip.
Attempts are now under way to lower the source voltages of semiconductor integrated circuits including semiconductor memories. Flash memories are no exception, and such memories operating at lower than previous source voltages, for instance 3.3 V to 1.8 V, have come to be required. There are two types of flash memories, one type using hot electrons for writing into, and using the FN tunnel phenomenon for erasing any content from, memory cells and the other type using the FN tunnel phenomenon for both writing and erasion. The latter, using the FN tunnel phenomenon for both writing and erasion, requires a higher boosted voltage than the former.
In recent years, techniques regarding so-called multi-value memories, in which data of two or more bits are to be stored in a memory cell, have come to be proposed with a view to increasing the memory capacities of flash memories. In such multi-value memories, the threshold voltage is varied stepwise, for instance from 1 V to 2 V, 3 V and so forth and plural-bit information is stored, being matched with each threshold voltage, to control the quantity of electric charges injected into the floating gate. In order to set one memory cell to one of a plurality of threshold voltages and to read out the stored information accurately, it is necessary to provide some differences in potential in the distribution of the multiple threshold voltages, and consequently the overall potential difference in the distribution of threshold voltages becomes greater than for two-value memory cells. As a result, a higher boosted voltage is required in writing and erasion into and out of multi-value memories than in two-value memories.
A conventional voltage booster circuit using an ordinary charge pump involves a problem that the voltage cannot be boosted by no more than five times approximately, and boosting the voltage beyond a certain boosted level would suffer a sudden drop in efficiency, namely the saturation of boosted voltage.
There are two types of conventional charge pumps, a parallel capacity type as shown in FIG. 16 and a serial capacity type as shown in FIG. 17. Of the two types, a parallel capacity type charge pump shown in FIG. 16, first as shown in FIG. 16(A), charges up the capacities by applying a low source voltage Vss, such as a ground potential, to a first terminal (the lower terminal in the diagram) of a capacity C1 and a source voltage Vcc higher than Vss via a diode D1 to a second terminal (the upper terminal in the diagram). Then, as shown in FIG. 16(B), it operates so as to switch the voltage at the first terminal of the capacity C1 from the source voltage Vss to Vcc in a state wherein the source voltage Vss is applied to a first terminal of the adjoining capacity C2.
This results in voltage boosting of the second terminal of the capacity Cl to 2 Vcc and transfer to the charge on the capacity C1 to the capacity C2 via a diode D2. By repeating such operations to successively transfer charges on capacities, boosted voltages can be obtained, such as from 2 Vcc to 3 Vcc and to 4 Vcc. When the charge on the capacity C2 is to be transferred to the next stage, precharging for the next charge transfer at the capacity C1 of the first stage makes possible efficient voltage boosting. However, in a parallel capacity type charge pump, the presence of diodes intervening between the capacities invites a reduction of the transmitted voltages by as much as the voltages of these diodes in the forward direction.
It is conceivable to use switching elements, such as MOSFETs, instead of the diodes here, but also in that case, diode-connected MOSFETs, in which the gate and drain are coupled, the voltage will drop by as much as the threshold voltage. Or where switching MOSs are used, as is evident from FIG. 16, the voltage relationship between the source and drain of the switching MOSs is reversed. In other words, the source voltage may become either lower or higher than the drain voltage.
If, in an attempt to avoid it, P channel type switching MOSs are used, their well region will be of an N type, and if a configuration is so designed that the same voltage as in the source region, where the potential is high, be applied to the well region as in usual MOSFETs, when the potential in the drain region rises, the PN junction with the well region will be biased forward to let a current flow. Therefore, P channel type MOSFETs cannot be used. On the other hand, if N channel type switching MOSs are used, the transmitted voltage is reduced by as much as the threshold voltage of the MOSFETs because of their characteristics, and eventually it is difficult to boost the voltage without entailing a voltage drop.
A serial capacity type charge pump, as shown in FIG. 17, charges capacities C1, C2 and C3 in series in the same direction up to the source voltage Vcc with switches S1, S2 and S3 between the capacities C1, C2 and C3 kept in an off state as shown in FIG. 17(A). Then, as shown in FIG. 17(B), the switches S1, S2 and S3 between the capacities C1, C2 and C3 are turned on, and the charge pump is operated so as to switch the voltage of a first terminal (the left side terminal in the diagram) of a first capacity C1 from the source voltage Vss to Vcc. Then, the voltage of a second terminal of the capacity C1 will rise to 2 Vcc, and the voltages of second terminals of capacities C2 and C3 will rise to 3 Vcc and 4 Vcc as, though the inter-terminal voltages of the capacities C2 and C3 are respectively charged source voltages Vcc, the voltage of each first terminal is switched from Vss to the voltage of the second terminal of the adjoining capacity. Thus, boosted voltages are obtained.
However, while it is effective in reducing the capacity size, in a serial capacity charge pump, to use capacities between the well region and the gate region, utilizing the gate oxide film of MOSFET, which is the thinnest among all the capacities, the actual circuit of such a configuration in this case would be such that capacities Cs of PN junction between the well region and the substrate are connected to capacities C1, C2 and C3 as shown in FIG. 17. As a result, when switches S1, S2 and S3 between the capacities C1, C2 and C3 are turned on, part of the charges on the capacity at the preceding stage is consumed to charge the parasitic capacity Cs of the next stage, and the boosted voltage will be reduced correspondingly.
According to what the present inventors studied, a multi-value flash memory requires a high voltage of ∓16 V or more for writing into and erasing any content out of memory cells, and it has been revealed that, where the source voltage is 1.8 V, a booster circuit capable of generating a voltage 10 times as high as thee source voltage, or even higher, will be needed.
Then, the inventors thought a high boosted voltage could be generated by combining the aforementioned two types of charge pumps, and studied this concept. They arrived at an idea that by using a parallel capacity type charge pump for the first stage of voltage boosting and a serial capacity type charge pump for the second stage of voltage boosting, a high boosted voltage could be obtained. Incidentally, inventions regarding the generation of a boost voltage by combining two or more charge pumps are disclosed in, for instance, the Japanese Unexamined Patent Applications Nos. Hei 3(1991)-73565, 5(1993)-28785 and 6(1994)-208798 (U.S. Pat. No. 5,280,420).
However, any of the prior inventions providing for a combination of two or more charge pumps either specifies the types of charge pumps to be combined or the combination of parallel capacity type charge pumps alone, but none achieves so high a boosted voltage that charge pumps of any single type can attain by tactfully combining charge pumps of the pump parallel capacity and serial capacity types to take advantage of the strong points of both.
An object of the present invention is to provide a voltage booster circuit, for use in a semiconductor integrated circuit having an internal booster circuit such as a flash memory, capable of generating a boosted voltage 10 times or more as high as a relatively low source voltage.
Another object of the invention is to provide a voltage booster circuit, for use in a semiconductor integrated circuit having an internal booster circuit such as a flash memory, capable of efficiently generating a boosted voltage by discriminatively using one or another of different types of charge pumps according to the type of the circuit to receive the supply of the boosted voltage generated by the booster circuit.
Still another object of the invention is to reduce the consumption of power by a semiconductor integrated circuit having an internal booster circuit such as a flash memory by selectively operating charge pumps according to the operating mode.
Yet another object of the invention is to provide a voltage booster circuit, for use in a semiconductor integrated circuit having an internal booster circuit such as a flash memory, capable of generating a stable boosted voltage irrespective of the levels of source voltage and power consumption.
These and other objects and novel features of the present invention will become apparent from the description in this specification when taken in conjunction with the accompanying drawings.
Typical aspects of the invention disclosed in this application will be summarized below.
Thus, in a semiconductor integrated circuit provided with an internal booster circuit, a charge pump for carrying out voltage boosting of a first stage based on a source voltage is configured of a parallel capacity type unit and another charge pump for carrying out voltage boosting of a second stage based on the boosted voltage generated by the foregoing charge pump is configured of a serial capacity type unit.
A serial capacity type charge pump has characteristic in which it is easy to design from its voltage resistance aspect because voltages applied to voltage boosting capacities of different stages arranged in series are substantially equal though, with an increase in the number of stages, the voltage reached quickly saturates as charges are spent by parasitic capacities. On the other hand, a parallel capacity type charge pump has characteristic in which it is less subject to saturation of the boosted voltage than the serial capacity type even if the number of stages is somewhat large though its voltage resistance is not sufficient to be compatible with a high boosted voltage because voltages applied to voltage boosting capacities of different stages arranged in parallel differ from one another and are higher in later stages. Therefore, by configuring the charge pump for voltage boosting at the first stage of a parallel capacity type unit and configuring the charge pump for voltage boosting at the second stage of a serial capacity type unit, a relatively high boosted voltage can be generated more efficiently than in a reverse case.
More preferably, the parallel capacity type charge pump for the first stage of voltage boosting should be provided in divided units according to the types of circuits to which the generated voltage is supplied. More specifically, it is preferable to provide separate charge pumps according to the type of the types of circuits to which the generated voltage is supplied, differentiated between a capacitive load and a resistive load.
The configuration described above permits control to reduce power consumption by stopping the operation of one of the charge pumps according to the mode of operation or by switching the frequency of operating clocks, and to reliably generate a boosted voltage of a desired level even if the source voltage is low.
Further, the parallel capacity type charge pump for the first stage of voltage boosting may be configured of capacities each using a gate insulating film differing in thickness from the others, the thickness increasing with the level of the boosted voltage. This makes it possible for capacities on the lower voltage side to occupy less space to achieve a prescribed capacitance because of their smaller insulating film thickness and capacities on the higher voltage side to be made more resistant to voltage by their greater insulting film thickness, resulting in assured reliability.
In particular in a nonvolatile memory, such as a flash memory, wherein memory cells are configured of MOSFETs of a double gate structure having a floating gate and a control gate, a first gate insulating film (tunnel insulating film) under the floating gate is formed thinner than a second gate insulating film between the floating gate and the control gate, and therefore these gate insulating films are used as two types of insulating films for capacities within the charge pump. In this way, a charge pump having capacities using two different types of insulating films can be realized and any additional cost can be avoided.
Further, where the level of the externally supplied source voltage drops of the power consumption of the parallel capacity type charge pump for the first stage of voltage boosting increases, control is so effected as to lower the frequency of signals to operate the serial capacity type charge pump for the second stage of voltage boosting, such as clock signals. This ensures appropriate operation both in circuits running on the boosted voltage from the charge pump for the first stage of voltage boosting and in circuits running on the boosted voltage from the charge pump for the second stage of voltage boosting.
Moreover, in a semiconductor integrated circuit such as a flash memory, circuits running on the boosted voltage of the second stage are circuits for write and erasion and, only if the voltage level is assured for them, no fatal trouble can occur even if some time is taken to reach a desired level. On the other hand, the undesirable eventuality that chips are prevented from operating by the failure of the boosted voltage to attain the target level can be averted, because the boosted voltage can reach the desired level even if it has to be awaited for some time.